As semiconductor devices have become more highly integrated, the size of features in the semiconductor devices and the spacings therebetween have been reduced. As a result, the pitch of the various patterns used to form the device features have been scaled-down. However, it has become increasingly difficult to form sufficiently fine line and space patterns (hereinafter referred to as “L/S patterns”) on various substrate materials due to the resolution limitations of conventional photolithography processes used to form the patterns.
One of the ways that these semiconductor devices have been more highly integrated is through the use of a photolithography process sometimes referred to as self-aligned reverse patterning (SARP) to form relatively fine patterns having a relatively fine pitch. According to the self-aligned reverse patterning approach, a pattern can be formed on a layer in which features (a feature layer) are to be formed. A conformal layer can be formed on the pattern and subsequently removed from the feature layer and the pattern, except that portions of the conformal layer can remain on sidewalls of the pattern. Then, the pattern can be removed from the feature layer such that the portions of the conformal layer on the sidewalls remain. The remaining portions of the conformal layer can define a mask pattern that can be used to etch a reverse pattern into the feature layer.
The use of photolithography to form patterns for use in the manufacture of semiconductor devices is also discussed in, for example, U.S. Pat. Nos. 6,475,891; 6,723,607; 7,115,525; and 7,253,118.